CHAPTER 6 CLOCK GENERATION FUNCTION
User’s Manual U15905EJ2V1UD
204
(1) Main clock oscillator
This circuit oscillates the following frequency (fX):
2 to 20 MHz (at 2.2 to 2.7 V operation)
(2) Subclock oscillator
This circuit oscillates a frequency of 32.768 kHz (fXT).
(3) Main clock resonator stop control
This circuit generates a control signal that stops oscillation of the main clock resonator.
It stops the oscillation of the main clock resonator in the software STOP mode or when the MCK bit = 1 (valid
only when the CLS bit = 1).
(4) Prescaler 1
This circuit generates the clock (fXX to fXX/512) to be supplied to the internal peripheral functions.
The clock is supplied to the following blocks:
TM0 to TM5, CSI0 to CSI4, UART0, UART1, I
2C, ADC, DAC
(5) Prescaler 2
This circuit divides the main clock (fXX).
The clock generated by prescaler 2 (fXX to fXX/32) is supplied to the selector that generates the internal system
clock (fCLK).
fCLK is the clock that is supplied to the CPU, INTC, DMAC, and ROMC blocks, and can be output from the
CLKOUT pin.
(6) Prescaler 3
This circuit divides the clock (fX) generated by the main resonator to a specific frequency (32.768 kHz) and
supplies it to the RTC and ADC.
For details, refer to 6.5 Prescaler 3.
(7) Watchdog timer clock control
This circuit generates the clock (fXW) to be supplied to the watchdog timer.
The watchdog timer is used alternately as the oscillation stabilization timer, so the source clock is automatically
switched according to the operation status shown below.
From software STOP mode or RESET pin input to when oscillation stabilization time has been counted: fX
Other than above: fXX
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